Verification of COMBO6 VHDL Design
| Authors | |
|---|---|
| Year of publication | 2003 |
| Type | R&D Presentation |
| MU Faculty or unit | |
| Citation | |
| Description | This technical report presents current results and experiences of the formal verification of VHDL design of Combo6 hardware accelerator card. Information about formal verification itself is enriched by description of transformation from VHDL to the Cadence SMV specification language and the system of assertions established as a compact way of communication with VHDL designers. |
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